As large-scale integrated (LSI) circuits develop into very large-scale integrated (VLSI) circuits, the number of combinational logics included in an integrated circuit has increased. A scan path is used to verify the integrity of the combinational logic in a VLSI circuit. However, the scan path may increase power consumption of an integrated circuit, and may cause reduction of the operating speed. As the number of transistors integrated in a single integrated circuit increases, leakage power consumption is becoming an important issue.